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DS002 (v1.2) February 13, 2001
Preliminary Product Specification * Die-temperature sensing device
Features
* * * * Certified to MIL-PRF-38535 (Qualified Manufacturer Listing) Guaranteed over the full military temperature range (-55C to +125C) Ceramic and Plastic Packages Fast, high-density Field-Programmable Gate Arrays * * * Densities from 100K to 1M system gates System performance up to 200 MHz Hot-swappable for Compact PCI 16 high-performance interface standards Connects directly to ZBTRAM devices Four dedicated delay-locked loops (DLLs) for advanced clock control Four primary low-skew global clock distribution nets, plus 24 secondary global nets LUTs configurable as 16-bit RAM, 32-bit RAM, 16-bit dual-ported RAM, or 16-bit Shift Register Configurable synchronous dual-ported 4K-bit RAMs Fast interfaces to external high-performance RAMs Dedicated carry logic for high-speed arithmetic Dedicated multiplier support Cascade chain for wide-input functions Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset Internal 3-state bussing IEEE 1149.1 boundary-scan logic * * *
Supported by FPGA FoundationTM and Alliance Development Systems Complete support for Unified Libraries, Relationally Placed Macros, and Design Manager Wide selection of PC and workstation platforms Unlimited reprogrammability Four programming modes
SRAM-based in-system configuration
0.22 m 5-layer metal process 100% factory tested
Multi-standard SelectI/OTM interfaces
Description
The QPROTM VirtexTM FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 5-layer-metal 0.22 m CMOS process. These advances make QPRO Virtex FPGAs powerful and flexible alternatives to mask-programmed gate arrays. The Virtex family comprises the four members shown in Table 1. Building on experience gained from previous generations of FPGAs, the Virtex family represents a revolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the QPRO Virtex family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market. Refer to the "VirtexTM 2.5V Field Programmable Gate Arrays" commercial data sheet for more information on device architecture and timing specifications.
Built-in clock-management circuitry
Hierarchical memory system -
*
Flexible architecture that balances speed and density -
Table 1: QPRO Virtex Field-Programmable Gate Array Family Members Device XQV100 XQV300 XQV600 XQV1000 System Gates 108,904 322,970 661,111 1,124,022 CLB Array 20 x 30 32 x 48 48 x 72 64 x 96 Logic Cells 2,700 6,912 15,552 27,648 Maximum Available I/O 180 316 316 404 Block RAM Bits 40,960 65,536 98,304 131,072 Max Select RAM Bits 38,400 98,304 221,184 393,216
(c) 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS002 (v1.2) February 13, 2001 Preliminary Product Specification
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Virtex Electrical Characteristics
Based on preliminary characterization. Further changes are not expected. All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters included are common to popular designs and typical applications. Contact the factory for design considerations requiring more detailed information.
Virtex DC Characteristics
Absolute Maximum Ratings
Symbol VCCINT VCCO VREF VIN Supply voltage relative to GND Supply voltage relative to GND Input reference Voltage Input voltage relative to GND Using VREF Internal threshold VTS VCC TSTG TSOL TJ Voltage applied to 3-state output Longest supply voltage rise time from 1V to 2.375V Storage temperature (ambient) Maximum soldering temp. (10s at 1/16 in. = 1.5 mm) Junction temperature Ceramic packages Plastic packages Description Min/Max -0.5 to 3.0 -0.5 to 4.0 -0.5 to 3.6 -0.5 to 3.6 -0.5 to 5.5 -0.5 to 5.5 50 -65 to +150 +260 +150 +125 Units V V V V V V ms C C C C
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 2. Power supplies may turn on in any order. 3. For protracted periods (e.g., longer than a day), VIN should not exceed VCCO by more that 3.6V.
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Recommended Operating Conditions
Symbol VCCINT Description Supply voltage relative to GND, TC = -55C to +125C Supply voltage relative to GND, TJ = -55C to +125C VCCO Supply voltage relative to GND, TC = -55C to +125C Supply voltage relative to GND, TJ = -55C to +125C TIN TIC Input signal transition time Initialization Temperature Range4 XQVR300 XQVR600 XQVR1000 XQVR300 XQVR600 XQVR1000 Ceramic packages Plastic packages Ceramic packages Plastic packages Min 2.5 - 5% 2.5 - 5% 1.2 1.2 - 55 - 40 - 40 - 55 - 55 - 55 Max 2.5 + 5% 2.5 + 5% 3.6 3.6 250 +125 +125 +125 +125 +125 +125 Units V V V V ns C C C C C C
TOC
Operational Temperature Range 5
Notes: 1. Correct operation is guaranteed with a minimum VCCINT of 2.25V (Nominal VCCINT - 10%). Below the minimum value stated above, all delay parameters increase by 3% for each 50 mV reduction in VCCINT below the specified range. 2. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. 3. Input and output measurement threshold is ~50% of VCC. 4. Initialization occurs from the moment of VCC ramp-up to the rising transition of the INIT pin. 5. The device is operational after the INIT pin has transitioned high.
DC Characteristics Over Recommended Operating Conditions
Symbol VDRINT VDRIO ICCINTQ Description Data retention VCCINT voltage (below which configuration data may be lost) Data retention VCCO voltage (below which configuration data may be lost) Quiescent VCCINT supply current(1) Device All All XQV100 XQV300 XQV600 XQV1000 ICCOQ Quiescent VCCINT supply current(1) XQV100 XQV300 XQV600 XQV1000 IREF IL CIN IRPU IRPD VREF current per VREF pin Input or output leakage current Input capacitance (sample tested) Pad pull-up (when selected) at VIN = 0V, VCCO = 3.3V (sample tested) Pad pull-down (when selected) at VIN = 3.6V (sample tested) Min 2.0 1.2 -10 (2) (2)
Max 50 75 100 100 2 2 2 2 20 +10 8 0.25 0.15
Units V V mA mA mA mA mA mA mA mA A A pF mA mA
Notes: 1. With no output current loads, no active input pull-up resistors, all I/O pins in a High-Z state and floating. 2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors do not guarantee valid logic levels when input pins are connected to other circuits. DS002 (v1.2) February 13, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 3
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DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed output currents over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are Input/Output Standard LVTTL(1) LVCMOS2 PCI, 3.3 V PCI, 5.0 V GTL GTL+ HSTL I HSTL III HSTL IV SSTL3 I SSTL3 II SSTL2 I SSTL2 II CTT AGP VIL V, min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 V, max 0.8 0.7 44% VCCINT 0.8 VREF - 0.05 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.2 VREF - 0.2 VREF - 0.2 VREF - 0.2 VREF - 0.2 VREF - 0.2 V, min 2.0 1.7 60% VCCINT 2.0 VREF + 0.05 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.2 VREF + 0.2 VREF + 0.2 VREF + 0.2 VREF + 0.2 VREF + 0.2 VIH V, max 5.5 5.5 VCCO + 0.5 5.5 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 chosen to ensure that all standards meet their specifications. The selected standards are tested at minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. VOL V, Max 0.4 0.4 10% VCCO 0.55 0.4 0.6 0.4 0.4 0.4 VREF - 0.6 VREF - 0.8 VREF - 0.65 VREF - 0.80 VREF - 0.4 10% VCCO VOH V, Min 2.4 1.9 90% VCCO 2.4 n/a n/a VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VREF + 0.6 VREF + 0.8 VREF + 0.65 VREF + 0.80 VREF + 0.4 90% VCCO IOL mA 24 12
(2) (2)
IOH mA -24 -12
(2) (2)
40 36 8 24 48 8 16 7.6 15.2 8
(2)
n/a n/a -8 -8 -8 -8 -16 -7.6 -15.2 -8
(2)
Notes: 1. VOL and VOH for lower drive currents are sample tested. 2. Tested according to the relevant specifications.
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Virtex Switching Characteristics
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Virtex devices unless otherwise noted.
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values shown in "IOB Input Switching Characteristics Standard Adjustments" on page 6. Speed Grade Symbol
Propagation Delays
Description
Device
-4
Units
TIOPI TIOPID
Pad to I output, no delay Pad to I output, with delay
All XQV100 XQV300 XQV600 XQV1000
1.0 1.9 1.9 2.3 2.7 2.0 4.8 5.1 5.5 5.9
ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max
TIOPLI TIOPLID
Pad to output IQ via transparent latch, no delay Pad to output IQ via transparent latch, with delay
All XQV100 XQV300 XQV600 XQV1000
Sequential Delays
TIOCKIQ TIOPICK / TIOICKP TIOPICKD / TIOICKPD TIOICECK / TIOCKICE TIOSRCKI / TIOCKISR
Set/Reset Delays
Clock CLK to output IQ
All
0.8
Setup Time / Hold Time
ns, max
Setup and Hold Times with Respect to Clock CLK
Pad, no delay Pad, with delay ICE input SR input (IFF, synchronous)
All All All All
2.0 / 0 5.0 / 0 1.0 / 0 1.3 / 0
ns, min ns, min ns, min ns, min
TIOSRIQ TGSRQ
SR input to IQ (asynchronous) GSR to output IQ
All All
1.8 12.5
ns, max ns, max
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
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IOB Input Switching Characteristics Standard Adjustments
Speed Grade Symbol
Data Input Delay Adjustments
Description
Standard
-4
Units
TILVTTL TILVCMOS2 TIPCI33_3 TIPCI33_5 TIGTL TIGTLP TIHSTL TISSTL2 TISSTL3 TICTT TIAGP
Standard-specific data input delay adjustments
LVTTL LVCMOS2 PCI, 33 MHz, 3.3V PCI, 33 MHz, 5.0V GTL GTL+ HSTL SSTL2 SSTL3 CTT AGP
0.0 -0.05 -0.14 0.33 0.26 0.14 0.04 -0.10 -0.06 0.02 -0.08
ns ns ns ns ns ns ns ns ns ns ns
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IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in "IOB Output Switching page 8. Characteristics Standard Adjustments" on
Speed Grade Symbol
Propagation Delays
Description
-4
Units
TIOOP TIOOLP
3-State Delays
O input to pad O input to pad via transparent latch
3.5 4.0
ns, max ns, max
TIOTHZ TIOTON TIOTLPHZ TIOTLPON TGTS
Sequential Delays
T input to pad high-impedance(1) T input to valid data on pad T input to pad high-impedance via transparent latch(1)
2.4 3.7 3.0 4.2 6.3
ns, max ns, max ns, max ns, max ns, max
T input to valid data on pad via transparent latch GTS to pad high impedance(1)
TIOCKP TIOCKHZ TIOCKON
Clock CLK to pad Clock CLK to pad high-impedance (synchronous)(1) Clock CLK to valid data on pad (synchronous)
3.5 2.9 4.1
Setup Time / Hold Time(2)
ns, max ns, max ns, max
Setup and Hold Times before/after Clock CLK
TIOOCK/TIOCKO TIOOCECK/TIOCKOCE TIOSRCKO/TIOCKOSR TIOTCK/TIOCKT TIOTCECK/TIOCKTCE TIOSRCKT/TIOCKTSR
Set/Reset Delays
O input OCE input SR input (OFF) 3-state setup times, T input 3-state setup times, TCE input 3-state setup times, SR input (TFF)
1.3 / 0 1.0 / 0 1.4 / 0 0.9 / 0 1.1 / 0 1.3 / 0
ns, min ns, min ns, min ns, min ns, min ns, min
TIOSRP TIOSRHZ TIOSRON
SR input to pad (asynchronous) SR input to pad high-impedance (asynchronous)(1) SR input to valid data on pad (asynchronous)
4.6 3.9 5.1
ns, max ns, max ns, max
Notes: 1. High-impedance turn-off delays should not be adjusted. 2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
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IOB Output Switching Characteristics Standard Adjustments
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays by the values shown. Speed Grade Symbol
Output Delay Adjustments
Description
Standard
-4
Units
TOLVTTL_S2 TOLVTTL_S4 TOLVTTL_S6 TOLVTTL_S8 TOLVTTL_S12 TOLVTTL_S16 TOLVTTL_S24 TOLVTTL_F2 TOLVTTL_F4 TOLVTTL_F6 TOLVTTL_F8 TOLVTTL_F12 TOLVTTL_F16 TOLVTTL_F24 TOLVCMOS2 TOPCI33_3 TOPCI33_5 TOGTL TOGTLP TOHSTL_I TOHSTL_III TOHSTL_IV TOSSTL2_I TOSSTL2_II TOSSTL3_I TOSSTL3_II TOCTT TOAGP
Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, Csl)
LVTTL, slow
2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA
17.0 8.6 5.6 3.5 2.2 2.0 1.6 15.1 6.1 3.6 1.2 0.0 -0.05 -0.23 0.12 2.7 3.3 0.6 1.0 -0.5 -1.0 -1.1 -0.5 -1.0 -0.5 -1.1 -0.6 -1.0
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
LVTTL, fast
2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA
LVCMOS2 PCI, 33 MHz, 3.3V PCI, 33 MHz, 5.0V GTL GTL+ HSTL I HSTL III HSTL IV SSTL2 I SSTL2 II SSTL3 I SSTL3 II CTT AGP
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Calculation of Tioop as a Function of Capacitance
The values for Tioop were based on the standard capacitive load (Csl) for each I/O standard as listed in Table 2. For other capacitive loads, use the formulas below to calculate the corresponding Tioop: Tioop = Tioopl + Topadjust + (Cload - Csl) * fl Where: Topadjust is reported above in the Output Delay Adjustment section. Cload is the capacitive load for the design. Table 2: Constants for Use in Calculation of Top Standard LVTTL slow slew rate 2 mA drive 4 mA drive 6 mA drive 8 mA drive 12 mA drive 16mA drive 24 mA drive LVTTL fast slew rate 2 mA drive 4 mA drive 6 mA drive 8 mA drive 12 mA drive 16mA drive 24 mA drive Csl (pF) 35 35 35 35 35 35 35 35 35 35 35 35 35 35 fl (ns/pF) 0.41 0.20 0.100 0.086 0.058 0.050 0.048 0.41 0.20 0.13 0.079 0.044 0.043 0.033 Table 2: Constants for Use in Calculation of Top Standard LVCMOS2 PCI 33 MHz 5V PCI 33 MHZ 3.3V GTL GTL+ HSTL Class I HSTL Class III HSTL Class IV SSTL2 Class I SSTL2 Class II SSTL3 Class 1 SSTL3 Class II CTT AGP Csl (pF) 35 50 10 0 0 20 20 20 30 30 30 30 20 10 fl (ns/pF) 0.041 0.050 0.050 0.014 0.017 0.022 0.016 0.014 0.028 0.016 0.029 0.016 0.035 0.037
Clock Distribution Guidelines
Speed Grade Symbol
Global Clock Skew
Description Global clock skew between IOB flip-flops
Device XQV100 XQV300 XQV600 XQV1000
-4 0.15 0.18 0.17 0.25
Units ns, max ns, max ns, max ns, max
TGSKEWIOB
Notes: 1. These clock-distribution delays are provided for guidance only. They reflect the delays encountered in a typical design under worst-case conditions. Precise values for a particular design are provided by the timing analyzer.
Clock Distribution Switching Characteristics
Speed Grade Symbol
GCLK IOB and Buffer
Description Global clock pAD to output Global clock buffer I input to O output
-4 0.9 0.9
Units ns, max ns, max
TGPIO TGIO
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CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise values are provided by the timing analyzer. Speed Grade Symbol
Combinatorial Delays
Description
-4
Units
TILO TIF5 TIF5X TIF6Y TF5INY TIFNCTL TBYYB
Sequential Delays
4-input function: F/G inputs to X/Y outputs 5-input function: F/G inputs to F5 output 5-input function: F/G inputs to X output 6-input function: F/G inputs to Y output via F6 MUX 6-input function: F5IN input to Y output Incremental delay routing through transparent latch to XQ/YQ outputs BY input to YB output
0.8 0.9 1.0 1.2 0.5 0.8 0.7
ns, max ns, max ns, max ns, max ns, max ns, max ns, max
TCKO TCKLO
FF clock CLK to XQ/YQ outputs Latch clock CLK to XQ/YQ outputs
1.4 1.6
Setup Time / Hold Time
ns, max ns, max
Setup and Hold Times before/after Clock CLK
TICK/TCKI TIF5CK/TCKIF5 TF5INCK/TCKF5IN TIF6CK/TCKIF6 TDICK/TCKDI TCECK/TCKCE TRCKTCKR
Clock CLK
4-input function: F/G Inputs 5-input function: F/G inputs 6-input function: F5IN input 6-input function: F/G inputs via F6 MUX BX/BY inputs CE input SR/BY inputs (synchronous)
1.5 / 0 1.7 / 0 1.2 / 0 1.9 / 0 0.8 / 0 1.0 / 0 0.9 / 0
ns, min ns, min ns, min ns, min ns, min ns, min ns, min
TCH TCL
Set/Reset
Minimum pulse width, High Minimum pulse width, Low
2.0 2.0
ns, min ns, min
TRPW TRQ TIOGSRQ
Minimum pulse width, SR/BY inputs Delay from SR/BY inputs to XQ/YQ outputs (asynchronous) Delay from GSR to XQ/YQ outputs
3.3 1.4 12.5
ns, min ns, max ns, max
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
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CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. Precise values are provided by the timing analyzer. Speed Grade Symbol
Combinatorial Delays
Description
-4
Units
TOPX TOPXB TOPY TOPYB TOPCYF TOPGY TOPGYB TOPCYG TBXCY TCINX TCINXB TCINY TCINYB TBYP
Multiplier Operation
F operand inputs to X via XOR F operand input to XB output F operand input to Y via XOR F operand input to YB output F operand input to COUT output G operand inputs to Y via XOR G operand input to YB output G operand input to COUT output BX initialization input to COUT CIN input to X output via XOR CIN input to XB CIN input to Y via XOR CIN input to YB CIN input to COUT output
1.0 1.4 2.0 2.0 1.5 1.2 2.1 1.6 1.1 0.6 0.1 0.6 0.6 0.2
ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max ns, max
TFANDXB TFANDYB TFANDCY TGANDYB TGANDCY
F1/2 operand inputs to XB output via AND F1/2 operand inputs to YB output via AND F1/2 operand inputs to COUT output via AND G1/2 operand inputs to YB output via AND G1/2 operand inputs to COUT output via AND
0.5 1.1 0.6 0.7 0.2
Setup Time / Hold Time
ns, max ns, max ns, max ns, max ns, max
Setup and Hold Times before/after Clock CLK
TCCKX/TCKCX TCCKY/TCKCY
CIN input to FFX CIN input to FFY
1.3 / 0 1.4 / 0
ns, min ns, min
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
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CLB SelectRAM Switching Characteristics
Speed Grade Symbol
Sequential Delays
Description Clock CLK to X/Y outputs (WE active) Clock CLK to X/Y outputs
-4 3.0 3.0
Setup Time / Hold Time
Units ns, max ns, max
TSHCKO TSHCKO
Shift-Register Mode
Setup Times before Clock CLK
TAS/TAH TDS/TDH TWS/TWH TSHDICK TSHCECK
Clock CLK
F/G address inputs BX/BY data inputs (DIN) CE input (WE) BX/BY data inputs (DIN) CE input (WS) Minimum pulse width, High Minimum pulse width, Low Minimum clock period to meet address write cycle time Minimum pulse width, High Minimum pulse width, Low
0.7 / 0 0.9 / 0 1.0 / 0 0.9 1.0 3.1 3.1 6.2 3.1 3.1
ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min ns, min
Shift-Register Mode
TWPH TWPL TWC TSRPH TSRPL
Shift-Register Mode
Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
BLOCKRAM Switching Characteristics
Speed Grade Symbol
Sequential Delays
Description Clock CLK to DOUT output ADDR inputs DIN inputs EN input RST input WEN input Minimum pulse width, High Minimum pulse width, Low CLKA -> CLKB setup time for different ports
-4 4.1 1.5 / 0 1.5 / 0 3.4 / 0 3.2 / 0 3.0 / 0 2.0 2.0 4.0
Units ns, max ns, min ns, min ns, min ns, min ns, min ns, min ns, min
TBCKO TBACK/TBCKA TBDCK/TBCKD TBECK/TBCKE TBRCK/TBCKR TBWCK/TBCKW
Clock CLK
Setup Times Before Clock Clk
TBPWH TBPWL TBCCS
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TBUF Switching Characteristics
Speed Grade Symbol
Combinatorial Delays
Description
-4
Units
TIO TOFF TON
IN input to OUT output TRI input to OUT output high-impedance Tri input to valid data on OUT output
0.0 0.2 0.2
ns, max ns, max ns, max
JTAG Test Access Port Switching Characteristics
Speed Grade Symbol TTAPTCK TTCKTAP TTCKTDO FTCK Description TMS and TDI setup times before TCK TMS and TDI hold times after TCK Output delay from clock TCK to output TDO Maximum TCK clock frequency -4 4.0 2.0 11.0 33 Units ns, min ns, min ns, max MHz, max
Virtex Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL
Speed Grade Symbol Description LVTTL Global Clock Input to Output Delay using Output Flip-flop, 12 mA, Fast Slew Rate, with DLL. For data output with different standards, adjust the delays with the values shown in "IOB Output Switching Characteristics Standard Adjustments" on page 8. Device XQV100 XQV300 XQV600 XQV1000 -4 3.6 3.6 3.6 3.6 Units ns, max ns, max ns, max ns, max
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For different loads, see Table 2. 3. DLL output jitter is already included in the timing calculation.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL
Speed Grade Symbol Description LVTTL Global Clock Input to Output Delay using Output Flip-flop, 12 mA, Fast Slew Rate, without DLL. For data output with different standards, adjust the delays with the values shown in "IOB Output Switching Characteristics Standard Adjustments" on page 8. Device XQV100 XQV300 XQV600 XQV1000 -4 5.7 5.9 6.0 6.3 Units ns, max ns, max ns, max ns, max
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For different loads, see Table 2. DS002 (v1.2) February 13, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 13
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Minimum Clock to Out for Virtex Devices
With DLL I/O Standard LVTTL_S2(1) LVTTL_S4(1) LVTTL_S6(1) LVTTL_S8(1) LVTTL_S12(1) LVTTL_S16(1) LVTTL_S24(1) LVTTL_F2(1) LVTTL_F4(1) LVTTL_F6(1) LVTTL_F8(1) LVTTL_F12(1) LVTTL_F16(1) LVTTL_F24(1) LVCMOS2 PCI33_3 PCI33_5 GTL GTL+ HSTL I HSTL III HSTL IV SSTL2 I SSTL2 II SSTL3 I SSTL3 II CTT AGP All Devices 5.2 3.5 2.8 2.2 2.0 1.9 1.8 2.9 1.7 1.2 1.1 1.0 0.9 0.9 1.1 1.5 1.4 1.6 1.7 1.1 0.9 0.8 0.9 0.8 0.8 0.7 1.0 1.0 V100 6.0 4.3 3.6 3.1 2.9 2.8 2.6 3.8 2.6 2.0 1.9 1.8 1.8 1.7 1.9 2.4 2.2 2.5 2.5 1.9 1.7 1.6 1.7 1.6 1.7 1.5 1.8 1.8 V300 6.1 4.4 3.7 3.1 2.9 2.8 2.7 3.8 2.6 2.1 2.0 1.9 1.8 1.8 2.0 2.4 2.3 2.5 2.6 2.0 1.8 1.7 1.8 1.7 1.7 1.6 1.9 1.9 Without DLL V600 6.1 4.4 3.7 3.2 3.0 2.9 2.7 3.9 2.7 2.1 2.0 1.9 1.8 1.8 2.0 2.5 2.3 2.6 2.6 2.0 1.8 1.7 1.8 1.7 1.7 1.6 1.9 1.9 V1000 6.1 4.4 3.7 3.2 3.0 2.9 2.8 3.9 2.7 2.2 2.0 1.9 1.9 1.9 2.1 2.5 2.4 2.6 2.7 2.0 1.9 1.8 1.8 1.7 1.8 1.7 2.0 2.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. S = Slow Slew Rate, F = Fast Slew Rate 2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column. and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 3. Output timing is measured at 50% VCC threshold with 8 pF external capacitive load.
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QPRO Virtex 2.5V QML High-Reliability FPGAs
Virtex Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock loading. Values are expressed in nanoseconds unless otherwise noted
Global Clock Setup and Hold for LVTTL Standard, with DLL
Speed Grade Symbol Description Device -4 Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different standards, adjust the setup time delay by the values shown in Input Delay Adjustments. TPSDLL/TPHDLL
No Delay
XQV100 XQV300 XQV600 XQV1000
2.1 / -0.4 2.1 / -0.4 2.1 / -0.4 2.1 / -0.4
ns, min ns, min ns, min ns, min
Global clock and IFF, with DLL
Notes: 1. IFF = Input Flip-Flop or Latch 2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 3. DLL output jitter is already included in the timing calculation.
Global Clock Setup and Hold for LVTTL Standard, without DLL
Speed Grade Symbol Description Device -4 Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different standards, adjust the setup time delay by the values shown in Input Delay Adjustments. TPSFD/TPHFD
Full Delay
XQV100 XQV300 XQV600 XQV1000
3.0 / 0.0 3.1 / 0.0 3.3 / 0.0 3.6 / 0.0
ns, min ns, min ns, min ns, min
Global clock and IFF, without DLL
Notes: 1. IFF = Input Flip-Flop or Latch 2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time.
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DLL Timing Parameters
Switching parameters testing is modeled after testing methods specified by MIL-M-38510/605; all devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case values across the recommended operating conditions. Speed Grade -4 Symbol FCLKINHF FCLKINLF TDLLPWHF TDLLPWLF Description Input clock frequency (CLKDLLHF) Inputclock frequency (CLKDLL) Input clock pulse width (CLKDLLHF) Input clock pulse width (CLKDLL) Min 60 25 2.4 3.0 Max 180 90 Units MHz MHz ns ns
Notes: 1. All specifications correspond to Commercial Operating Temperatures (0C to +100C).
CLKDLLHF Symbol TIPTOL TIJITCC TLOCK Description Input clock period tolerance Input clock jitter cycle to cycle Time required for DLL to acquire Lock FCLKIN > 60 MHz 50-60 MHz 40-50 MHz 30-40 MHz 25-30 MHz TSKEW TOPHASE TOJITCC DLL output skew (between any DLL output) DLL output long term phase differential DLL output ditter cycle to cycle 20 150 100 60 Min Max 1.0 150 -
CLKDLL Min Max 1.0 300 20 25 50 90 120 150 100 60 Units ns ps s s s s s ps ps ps
Notes: 1. All specifications correspond to Commercial Operating Temperatures (0C to +100C).
Period Tolerance: the allowed input clock period change in nanoseconds.
TCLKIN
TCLKIN + TIPTOL _
Clock Jitter: the difference between an ideal reference clock edgfe and the actual design.
+ TOJITCC
_
DS002_01_060100
Figure 1: Frequency Tolerance and Clock Jitter
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QPRO Virtex 2.5V QML High-Reliability FPGAs
QPRO Virtex Pinouts
Pinout Tables
See the Xilinx WebLINX web site (http://www.xilinx.com/partinfo/databook.htm) for updates or additional pinout information. For convenience, Table 3, Table 4 and Table 3: Virtex QFP Package Pinout Information Pin Name GCK0 GCK1 GCK2 GCK3 M0 M1 M2 CCLK PROGRAM DONE INIT BUSY/DOUT D0/DIN D1 D2 D3 D4 D5 D6 D7 WRITE CS TDI TDO TMS TCK VCCINT Device All All All All All All All All All All All All All All All All All All All All All All All All All All All PQ/HQ240 92 89 210 213 60 58 62 179 122 120 123 178 177 167 163 156 145 138 134 124 185 184 183 181 2 239 16, 32, 43, 77, 88, 104, 137, 148, 164, 198, 214, 225 No I/O Banks in this package: 15, 30, 44, 61, 76, 90, 105, 121, 136, 150, 165, 180, 197, 212, 226, 240 Table 5 list the locations of special-purpose and power-supply pins. Pins not listed are user I/Os.
VCCO
All
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QPRO Virtex 2.5V QML High-Reliability FPGAs Table 3: Virtex QFP Package Pinout Information (Continued) Pin Name VREF, Bank 0 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 1 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 2 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 3 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 4 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 5 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 6 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. XQV100 XQV300 XQV600 ... + 47 ... + 54 ... + 48 XQV100 XQV300 XQV600 ... + 73 ... + 66 ... + 72 XQV100 XQV300 XQV600 ... + 108 ... + 115 ... + 109 XQV100 XQV300 XQV600 ... + 133 ... + 126 ... + 132 XQV100 XQV300 XQV600 ... + 168 ... + 175 ... + 169 XQV100 XQV300 XQV600 ... + 194 ... + 187 ... + 193 Device XQV100 XQV300 XQV600 PQ/HQ240 ... + 229 ... + 236 ... + 230
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QPRO Virtex 2.5V QML High-Reliability FPGAs
Table 3: Virtex QFP Package Pinout Information (Continued) Pin Name VREF, Bank 7 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. GND Device XQV100 XQV300 XQV600 PQ/HQ240 ... + 12 ... + 5 ... + 11
All
1, 8, 14, 22, 29, 37, 45, 51, 59, 69, 75, 83, 91, 98, 106, 112, 119, 129, 135, 143, 151, 158, 166, 172, 182, 190, 196, 204, 211, 219, 227, 233
Table 4: Virtex Plastic Ball Grid and Ceramic Column Grid Pinout Information Pin Name GCK0 GCK1 GCK2 GCK3 M0 M1 M2 CCLK PROGRAM DONE INIT BUSY/DOUT D0/DIN D1 D2 D3 D4 D5 D6 D7 WRITE CS TDI TDO TMS TCK DXN Device All All All All All All All All All All All All All All All All All All All All All All All All All All All BG256 Y11 Y10 A10 B10 Y1 U3 W2 B19 Y20 W19 U18 D18 C19 E20 G19 J19 M19 P19 T20 V19 A19 B18 C17 A20 D3 A1 W3 BG352 AE13 AF14 B14 D14 AD24 AB23 AC23 C3 AC4 AD3 AD2 E4 D3 G1 J3 M3 R3 U4 V3 AC3 D5 C4 B3 D4 D23 C24 AD23 BG432 AL16 AK16 A16 D17 AH28 AH29 AJ28 D4 AH3 AH4 AJ2 D3 C2 K4 K2 P4 V4 AB1 AB3 AG4 B4 D5 B3 C4 D29 D28 AH27 BG560/CG560 AL17 AJ17 D17 A17 AJ29 AK30 AN32 C4 AM1 AJ5 AH5 D4 E4 K3 L4 P3 W4 AB5 AC4 AJ4 D6 A2 D5 E6 B33 E29 AK29
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QPRO Virtex 2.5V QML High-Reliability FPGAs Table 4: Virtex Plastic Ball Grid and Ceramic Column Grid Pinout Information (Continued) Pin Name DXP VCCINT (VCCINT pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Device All XQV100 BG256 V4 C10, D6, D15, F4, F17, L3, L18, R4, R17, U6, U15, V10 A20, B16, C14, D10, D12, J24, K4, L1, L25, P2, P25, R23, T1, V24, W2, AC10, AE14, AE19, AF11, AF16, A10, A17, B23, C14, C19, K3, K29, N2, N29, T1, T29, W2, W31, AB2, AB30, AJ10, AJ16, AK13, AK19, AK22 ... + B26, C7, F1, F30, AE29, AF1, AH8, AH24 A21, B12, B14, B18, B28, C22, C24, E9, E12, F2, H30, J1, K32, M3, N1, N29, N33, U5, U30, Y2, Y31, AB2, AB32, AD2, AD32, AG3, AG31, AJ13, AK8, AK11, AK17, AK20, AL14, AL22, AL27, AN25 D7, D8 D13, D14 G17, H17 N17, P17 U13, U14 U7, U8 A17, B25, D19 A10, D7, D13 B2, H4, K1 P4, U1, Y4 AC8, AE2, AF10 AC14, AC20, AF17 U26, W23, AE25 G23, K26, N23 A21, C29, D21 A1, A11, D11 C3, L1, L4 AA1, AA4, AJ3 AH11, AL1, AL11 AH21, AJ29, AL21 AA28, AA31, AL31 A31, L28, L31 A22, A26, A30, B19, B32 A10, A16, B13, C3, E5 B2, D1, H1, M1, R2 V1, AA2, AD1, AK1, AL2 AM2, AM15, AN4, AN8, AN12 AL31, AM21, AN18, AN24, AN30 W32, AB33, AF33, AK33, AM32 C32, D33, K33, N32, T33 BG352 AE24 BG432 AK29 BG560/CG560 AJ28
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XQV300
XQV600
XQV1000
VCCO, Bank 0 VCCO, Bank 1 VCCO, Bank 2 VCCO, Bank 3 VCCO, Bank 4 VCCO, Bank 5
All All All All All All
VCCO, Bank 6
All
N4, P4
VCCO, Bank 7
All
G4, H4
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QPRO Virtex 2.5V QML High-Reliability FPGAs
Table 4: Virtex Plastic Ball Grid and Ceramic Column Grid Pinout Information (Continued) Pin Name VREF, Bank 0 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 1 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 2 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 3 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. Device XQV100 XQV300 XQV600 XQV1000 BG256 A4, A8, B4 A16, C19, C21, D21 B19, D22, D24, D26 ... + C18, C24 A19, D20, D26, D29, E21, E23, E24, E27, A17, B12, B15 B6, C9, C12, D6 A13, B7, C6, C10 ... + B15, D10 A6, D7, D10, D11, D13, D16, E7, E15 C20, F19, J18 D2, E2, H2, M4 E2, G3, J2, N1 ... + H1, R3 B3, G5, H4, K5, L5, N5, P4, R1 BG352 BG432 BG560/CG560
XQV100 XQV300 XQV600 XQV1000
XQV100 XQV300 XQV600 XQV1000
XQV100 XQV300 XQV600 XQV1000
M18, R19, V20 R4, V4, Y3, AC2 V2, AB4, AD4, AF3 ... + U2, AC3 V4, W5, AA4, AD3, AE5, AF1, AH4, AK2
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QPRO Virtex 2.5V QML High-Reliability FPGAs Table 4: Virtex Plastic Ball Grid and Ceramic Column Grid Pinout Information (Continued) Pin Name VREF, Bank 4 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 5 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. Device XQV100 XQV300 XQV600 XQV1000 BG256 V12, W15, Y18 AC12, AE4, AE5, AE8 AJ7, AL4, AL8, AL13 ... + AK8, AK15 AK13, AL7, AL9, AL10, AL16, AM4, AM14,AN3 V9, W6, Y3 AC15, AC18, AD20, AE23 AJ18, AJ25, AK23, AK27 ... + AJ17, AL24 AJ18, AJ25, AK28, AL20, AL24, AL29, AM26, AN23 M2, R3, T1 R24, Y26, AA25, AD26 V28, AB28, AE30, AF28 ... + U28, AC28 V29, Y32, AA30,AD31, AE29, AK32, AE31, AH30 D1, G3, H1 D26, E24, G26, L26 F28, F31, J30, N30 ... + J28, R31 D31, E31, G31, H32, K31, P31, T31 BG352 BG432 BG560/CG560
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XQV100 XQV300 XQV600 XQV1000
VREF, Bank 6 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 7 (VREF pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Within each bank, if input reference voltage is not required, all VREF pins are general I/O.
XQV100 XQV300 XQV600 XQV1000
XQV100 XQV300 XQV600 XQV1000
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QPRO Virtex 2.5V QML High-Reliability FPGAs
Table 4: Virtex Plastic Ball Grid and Ceramic Column Grid Pinout Information (Continued) Pin Name GND Device All BG256 C3, C18, D4, D5, D9, D10, D11, D12, D16, D17. E4, E17, J4, J17, K4, K17, L4, L17, M4, M9, M10, M17, T4, T17, U4, U5, U9, U10, U11, U12, U16, U17, V3, V18 BG352 A1, A2, A5, A8, A14, A19, A22, A25, A26, B1, B26, E1, E26, H1, H26, N1, P26, W1, W26, AB1, AB26, AE1, AE26, AF1, AF2, AF5, AF8, AF13, AF19, AF22, AF25, AF26 BG432 A2, A3, A7, A9, A14, A18, A23, A25, A29, A30, B1, B2, B30, B31, C1, C31, D16, G1, G31, J1, J31, P1, P31, T4, T28, V1, V31, AC1, AC31, AE1, AE31, AH16, AJ1, AJ31, AK1, AK2, AK30, AK31, AL2, AL3, AL7, AL9, AL14, AL18, AL23, AL25, AL29, AL30 BG560/CG560 A1, A7, A12, A14, A18, A20, A24, A29, A32, A33, B1, B6, B9, B15, B23, B27, B31, C2, E1, F32, G2, G33, J32, K1, L2, M33, P1, P33, R32, T1, V33, W2, Y1, Y33, AB1, AC32, AD33, AE2, AG1, AG32, AH2, AJ33, AL32, AM3, AM7, AM11, AM19, AM25, AM28, AM33, AN1, AN2, AN5, AN10, AN14, AN16, AN20, AN22, AN27, AN33
GND(1)
All
J9, J10, J11, J12, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10, M11,M12 C31, AC2, AK4, AL3
No Connect
Notes: 1. 16 extra balls (grounded) at package center.
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Ceramic Quad Flat Package (CB228) Pinout Information
Table 5: CQFP Package (CB228) Function GND TMS IO IO IO_VREF_7 IO IO GND OIIO IO IO IO_VREF_7 IO GND VCCINT IO IO VCCO IO IO IO_VREF_7 IO IO IO IO IO_IRDY GND VCCO IO_TRDY VCCINT IO IO IO IO_VREF_6 IO IO VCCO IO Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Table 5: CQFP Package (CB228) (Continued) Function OP IO VCCINT GND IO IO_VREF_6 IO IO IO_VREF_6 GND IO IO IO_VREF_6 IO IO IO M1 GND M0 VCCO M2 IO IO IO IO_VREF_5 IO IO GND IO_VREF_5 IO IO IO_VREF5 IO GND VCCINT IO IO VCCO IO IO Pin No. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
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QPRO Virtex 2.5V QML High-Reliability FPGAs Table 5: CQFP Package (CB228) (Continued) Function IO IO_VREF_3 IO IO GND IO_VREF_3 IO IO IO_VREF_3 IO_D6 GND VCCINT IO_D5 IO VCCO IO IO IO_VREF_3 IO_D4 IO IO VCCINT IO_TRDY VCCO GND IO_IRDY IO IO IO IO_D3 IO_VREF_2 IO IO VCCO IO IO IO_D2 VCCINT GND IO_D1 Pin No. 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158
Table 5: CQFP Package (CB228) (Continued) Function IO_VREF_5 IO IO IO VCCINT GCK1 VCCO GND GCKO IO IO IO IO IO_VREF_4 IO IO VCCO IO IO IO VCCINT GND IO IO_VREF_4 IO IO IO_VREF_4 GND IO IO IO_VREF_4 IO IO IO GND DONE VCCO PROGRAM IO_INIT IO_D7 Pin No. 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118
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QPRO Virtex 2.5V QML High-Reliability FPGAs Table 5: CQFP Package (CB228) (Continued) Function IO_VREF_2 IO IO IO_VREF_2 GND IO IO IO_VREF_2 IO IO_DIN_D0 IO_DOUT_BUSY CCLK VCCO TDO GND TDI IO_CS IO_WRITE IO IO_VREF_1 IO GND IO_VREF_1 IO IO IO_VREF_1 IO GND VCCINT IO IO IO VCCO IO IO IO_VREF_1 IO IO IO IO Pin No. 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 VCCO VCCINT* Table 5: CQFP Package (CB228) (Continued) Function GCK2 GND VCCO GCK3 VCCINT IO IO IO IO_VREF_0 IO IO VCCO IO IO IO VCCINT GND IO IO_VREF_0 IO IO IO_VREF_0 GND IO IO IO_VREF_0 IO IO TCK VCCO GND* Pin No. 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 1, 8, 14, 27, 42, 48, 56, 66, 72, 86, 100, 106, 113, 123, 129, 143, 157, 163, 173, 180, 186, 200, 215, 221 15, 30, 41, 73, 83, 99, 130, 140, 156, 187, 203, 214 18, 28, 37, 58, 76, 85, 95, 115, 133, 142, 152, 171, 191, 201, 210, 228
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QPRO Virtex 2.5V QML High-Reliability FPGAs
Package Drawing CG560 Ceramic Column Grid
CG560 Ceramic Column Grid Package
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Device/Package Combinations and Maximum I/O
Maximum User I/O (Excluding dedicated clock pins.) Package PQ240 HQ240 BG256 BG352 BG432 BG560 CB228 CG560 XQV100 166 180 162 XQV300 166 316 162 XQV600 166 316 162 404 XQV1000 -
Ordering Information
Example:
Device Type
XQV300 -4 CB228 M
Temperature Range M = Military Ceramic (TC = -55C to +125C) N = Military Plastic (TJ = -55C to +125C) Number of Pins Package Type PQ = Plastic Quad Flat Pack HQ = High Heat Dissipation QFP (Plastic) BG = Plastic Ball Grid Array CB = Ceramic Quad Flat Pack CG = Ceramic Grid Column Array (Surface Mount)
Speed Grade
Revision History
The following table shows the revision history for this document Date 10/04/99 06/01/00 02/13/01 Version 1.0 1.1 1.2 Initial Xilinx release. Upated format. Updated Temperature Specifications. Revision
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DS002 (v1.2) February 13, 2001 Preliminary Product Specification

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